The motivation to reduce the magnitude of the power supply voltages on integrated FET circuits arises from the attempt to make FET circuits compatible with bipolar TTL circuits which operate at 5 volts instead of 8.5 volts and the use of processing technologies having closer line separations which require lower power supply voltages to avoid voltage induced faults. A complicating factor arises, however, in that the elimination of the 8.5 volt power supply voltage precludes the generation of a negative 5 volt potential for substrates employing the prior art substrate voltage generator circuit.
Prior art substrate voltage generator circuits include that disclosed in U.S. Pat. No. 3,806,741 to Smith, which discloses a conventional substrate voltage generator circuit requiring an 8.5 volt power supply to deliver a minus 5 volt substrate voltage. The use of static load devices such as R1-R6 generates a relatively high power dissipation and the circuit requires a substantial area for its layout on an integrated circuit chip. Since FET integrated circuits normally require a plus 5 volt voltage, the integrated circuit which employs this prior art voltage generator will require three voltages, a plus 8.5, a plus 5 and a ground voltage. If the prior art circuit had its operating input power supply voltage reduced to plus 5 volts, it would not be capable of generating minus 5 volts for the substrate voltage.